We will have a number of interesting speakers and also give a RISC-V overview! As it is a virtual conference we will make it 2h.
We plan some Q&A, you can submit questions during the presentation and we will answer them via chat or live from the speaker.
📅 AGENDA OVERVIEW
💻 A visual simulator for teaching computer architecture using the RISC-V instruction set
Guillaume Savaton , TBA
💻 Overview to CHIPS Alliance & RISC-V SweRV Cores
Zvonimir Bandic, Western Digital
💻 On-Chip Instrumentation – Debug & Trace, and On-Chip performance monitors
Gajinder Panesar, UltraSoC
💻 What’s missing in RISC-V Linux, how YOU can help!
Björn Töpel, RISC-V Enthusiast
We are still looking for speakers, so if you have an speech in the area of RISC-V feel free to contact us via Message or email florian (at) andestech (dot) com.
This time we think to limit it to 4 speaker but we already look for speaker for the next time, so feel free to submit your speech (or speech idea)