First virtual RISC-V Munich Meetup Date: April 29, 2020
📅 AGENDA OVERVIEW
💻 RISC-V International Overview
Calista Redmond, RISC-V International
💻 FPGA Benchmark leveraging RISC-V
Olof Kindgren, Fossi-Foundation
💻 RISC-V in Practical Education
Prof. Stefan Wallentowitz, Munich University of Applied Sciences
💻 RISC-V – insights from a commercial RISC-V supplier
Florian Wohlrab, Andes Technology
💻 RISC-V and Linux, an experience overview
Drew Fustini, Beagle Board
💻 Answering the RISC-V Questions that Users Are Asking
Sven Beyer, OneSpin Solutions
💻 High-Performance Multicore Application Processors with pre-integrated Trace and Debug
Jahoor Vohra, SiFive
Meetup Group : This group is for anyone interested in the open RISC-V ISA and related ecosystem..
RISC-V is a free ISA (Instruction Set Architecture) for a new bread of CPUs. It ranges from small CPU’s like found in Sensores for IoT over to Accerators and is also utilized in Datacenters. RISC-V is growing and will become more popular over the next years! The idea is to meet and talk about the possibilities of RISC-V and how to utilize it.
